Core i5 Processor

Native quad-core structure. Single processor die contains four cores with 256 KB L2 cache each and shared L3 cache; Elimination of the processor bus in its traditional form due to relocation of the PCI Express 2.0 controller directly into the CPU. This controller integrated into the processor provides support for 16 PCI Express 2.0 lanes, which can be used for one (in PCI Express x16 mode) or two (in PCI Express x8 mode) graphics cards.
Memory controller integrated into the CPU that supports dual-channel DDR3 SDRAM. Each memory channel can work with three unbuffered memory DIMMs. 8MB shared L3 cache. Integrated PCU microcontroller that independently controls the voltage and frequency of each core and can automatically overclock individual cores in case the remaining ones are not fully utilized. New SSE4.2 instructions support. Core i7-800 and Core i5-700 are manufactured with 45 nm process and consist of 774 million transistors on a 296 mm2 die.